- Patent Title: Single phase fault isolation and restoration with loop avoidance
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Application No.: US16933630Application Date: 2020-07-20
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Publication No.: US11626753B2Publication Date: 2023-04-11
- Inventor: Erich Keller , Nicholas Carmine DiFonzo
- Applicant: G & W ELECTRIC COMPANY
- Applicant Address: US IL Bolingbrook
- Assignee: G & W ELECTRIC COMPANY
- Current Assignee: G & W ELECTRIC COMPANY
- Current Assignee Address: US IL Bolingbrook
- Agency: Michael Best & Friedrich LLP
- Main IPC: H02J13/00
- IPC: H02J13/00 ; H02J3/00 ; G01R31/08

Abstract:
Techniques for controlling a power distribution network are provided. An electronic processor receives, a fault indication associated with a fault from a first isolation device of a plurality of isolation devices. The processor identifies a first subset of a plurality of phases associated with the fault indication and a second subset of the plurality of phases not associated with the fault indication. The processor identifies a downstream isolation device downstream of the fault. The processor sends send a first open command to the downstream isolation device for each phase in the first subset. The processor sends a close command to a tie-in isolation device for each of the plurality of phases. The processor sends a second open command to the downstream isolation device for each phase in the second subset. Responsive to identifying a potential loop configuration, the processor sends the second open command prior to the close command.
Public/Granted literature
- US20220021237A1 SINGLE PHASE FAULT ISOLATION AND RESTORATION WITH LOOP AVOIDANCE Public/Granted day:2022-01-20
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