A variable delay circuit includes at least one first delay circuit and a second delay circuit. The first delay circuit includes multiple first delay elements connected in series and is configured to output a delay signal from a first stage first delay element that is a first stage of the first delay circuit. The second delay circuit includes at least one second delay element and multiple third delay elements connected in series. The second delay circuit is configured to output a delay signal from a first stage second delay element that is a first stage of the second delay circuit. The first stage first delay element and the first stage second delay element are connected in series. A delay signal obtained by delaying an input signal received at one circuit among the first delay circuit and the second delay circuit for a predetermined time duration is output from another circuit.