A latchup immune microcontroller system with a power supply and a filter designed to eliminate external risks of triggering a latchup of a microcontroller caused by the power supply; a clock circuit with a clock frequency and a layout for eliminating external risks of triggering a latchup of the microcontroller caused by a high-frequency clock signal; a reset circuit that uses an optical triggering mechanism acting as a common power supply and an isolated power supply, the power detection circuit and a discharge circuit react in chain in time, avoid risks of triggering latchups of the microcontroller caused by reset signals; an interrupt with a high priority level and the discharge circuit react in chain in time to enhance data security, and output terminals are turned off in sequence to remove external causes of latchup. An application method of an I/O port to eliminate triggers of latchup of the microcontroller.