Invention Grant
- Patent Title: Method and system for enhanced multi-address read operations in low pin count interfaces
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Application No.: US17701044Application Date: 2022-03-22
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Publication No.: US11631441B2Publication Date: 2023-04-18
- Inventor: Kuen-Long Chang , Su-Chueh Lo , Yung-Feng Lin
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Andrew L. Dunlap
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G06F9/38 ; G06F9/445 ; G11C7/22

Abstract:
A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.
Public/Granted literature
- US20220215862A1 METHOD AND SYSTEM FOR ENHANCED MULTI-ADDRESS READ OPERATIONS IN LOW PIN COUNT INTERFACES Public/Granted day:2022-07-07
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