Invention Grant
- Patent Title: Method for manufacturing semiconductor structure
-
Application No.: US17643177Application Date: 2021-12-07
-
Publication No.: US11631656B2Publication Date: 2023-04-18
- Inventor: Hsih-Yang Chiu , Yi-Jen Lo
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L23/00 ; H01L25/00 ; H01L21/768

Abstract:
A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.
Public/Granted literature
- US20220102320A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Public/Granted day:2022-03-31
Information query
IPC分类: