Invention Grant
- Patent Title: Manufacturing method of semiconductor device and semiconductor device
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Application No.: US17060486Application Date: 2020-10-01
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Publication No.: US11631764B2Publication Date: 2023-04-18
- Inventor: Kenichi Hisada , Koichi Arai , Hironobu Miyamoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2018-046411 20180314
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/16 ; H01L29/66 ; H01L21/308 ; H01L29/08 ; H01L21/04 ; H01L21/02 ; H01L21/266
Abstract:
First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.
Public/Granted literature
- US20210028306A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2021-01-28
Information query
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