Invention Grant
- Patent Title: Synapse circuit and arithmetic device
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Application No.: US16287008Application Date: 2019-02-27
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Publication No.: US11636315B2Publication Date: 2023-04-25
- Inventor: Takao Marukame , Kumiko Nomura , Yoshifumi Nishi
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPJP2018-140290 20180726
- Main IPC: H03K3/02
- IPC: H03K3/02 ; H01L29/00 ; H03K19/00 ; G06N3/048 ; G06N3/08 ; G06N3/049 ; G06N3/063

Abstract:
According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
Public/Granted literature
- US20200034695A1 SYNAPSE CIRCUIT AND ARITHMETIC DEVICE Public/Granted day:2020-01-30
Information query
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