Invention Grant
- Patent Title: Memory cell array circuit and method of forming the same
-
Application No.: US17103239Application Date: 2020-11-24
-
Publication No.: US11636896B2Publication Date: 2023-04-25
- Inventor: Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C13/00
- IPC: G11C13/00
Abstract:
A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
Public/Granted literature
- US20210407594A1 MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME Public/Granted day:2021-12-30
Information query
