Invention Grant
- Patent Title: FinFET transistor cut etching process method
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Application No.: US16895083Application Date: 2020-06-08
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Publication No.: US11637194B2Publication Date: 2023-04-25
- Inventor: Yenchan Chiu , Yingju Chen , Liyao Liu , Chanyuan Hu
- Applicant: Shanghai Huali Integrated Circuit Corporation
- Applicant Address: CN Shanghai
- Assignee: Shanghai Huali Integrated Circuit Corporation
- Current Assignee: Shanghai Huali Integrated Circuit Corporation
- Current Assignee Address: CN Shanghai
- Agency: Banner & Witcoff, Ltd.
- Priority: CN201910986166.8 20191017
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/027 ; H01L21/306 ; H01L21/3065 ; H01L21/308 ; H01L29/16

Abstract:
The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.
Public/Granted literature
- US20210119023A1 FinFET Transistor Cut Etching Process Method Public/Granted day:2021-04-22
Information query
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