Invention Grant
- Patent Title: JFET with implant isolation
-
Application No.: US17131568Application Date: 2020-12-22
-
Publication No.: US11637209B2Publication Date: 2023-04-25
- Inventor: Clifford Drowley , Andrew P. Edwards , Subhash Srinivas Pidaparthi , Ray Milano
- Applicant: NEXGEN POWER SYSTEMS, INC.
- Applicant Address: US CA Santa Clara
- Assignee: NEXGEN POWER SYSTEMS, INC.
- Current Assignee: NEXGEN POWER SYSTEMS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L29/808
- IPC: H01L29/808 ; H01L29/66 ; H01L27/06 ; H01L29/20 ; H01L29/78 ; H01L29/06 ; H01L27/088
Abstract:
A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
Public/Granted literature
- US20210193846A1 METHOD AND SYSTEM FOR JFET WITH IMPLANT ISOLATION Public/Granted day:2021-06-24
Information query
IPC分类:
