Invention Grant
- Patent Title: Failure detection circuit and semiconductor device
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Application No.: US17016751Application Date: 2020-09-10
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Publication No.: US11639961B2Publication Date: 2023-05-02
- Inventor: Kenji Suina
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Tokyo; JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Tokyo; JP Tokyo
- Agency: Allen & Overy LLP
- Priority: JPJP2020-041695 20200311
- Main IPC: G01R31/317
- IPC: G01R31/317

Abstract:
A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.
Public/Granted literature
- US20210286005A1 FAILURE DETECTION CIRCUIT AND SEMICONDUCTOR DEVICE Public/Granted day:2021-09-16
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