Invention Grant
- Patent Title: Procedures for improving efficiency of an interconnect fabric on a system on chip
-
Application No.: US17228529Application Date: 2021-04-12
-
Publication No.: US11640362B2Publication Date: 2023-05-02
- Inventor: Shailendra Desai , Robert Totte , Juan Sierra , Parimal Gaikwad , Amit Jain , Mark Pearce
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Colby Nipper PLLC
- Main IPC: G06F13/20
- IPC: G06F13/20 ; G06F9/46 ; G06F9/48 ; G06F13/362 ; G06F13/366 ; G06F9/54 ; G06F13/40 ; G06F15/78

Abstract:
Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
Public/Granted literature
- US20210294762A1 PROCEDURES FOR IMPROVING EFFICIENCY OF AN INTERCONNECT FABRIC ON A SYSTEM ON CHIP Public/Granted day:2021-09-23
Information query