Data driving circuit, controller and display device for reducing load of circuits during high-speed driving
Abstract:
Embodiments of the present disclosure relate to a data driving circuit, a controller and a display device. A display driving is performed by outputting the number of internal data enable signals that is smaller than the number of external data enable signals in the display device performing high-speed driving. As a result, it is possible to prevent an increase in the load of the data driving circuit according to the high-speed driving. In addition, a part of the internal data enable signals is output during a blank period to prevent a decrease in the interval between the internal data enable signals and to increase the number of internal data enable signals. This can improve the image quality displayed on the display panel while preventing an increase in the load on the data driving circuit.
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