Semiconductor structures are provided. A first logic cell includes a plurality of first transistors over a substrate. The first transistor includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line in a first dielectric layer through a first contact in a second dielectric layer and a first via in the first dielectric layer. A second logic cell includes a plurality of second transistors over the substrate. The second transistor includes a second gate electrode across a second channel region, wherein the second gate electrode is electrically connected to a second conductive line in the first dielectric layer through a second via. The first dielectric layer is formed over the second dielectric layer, and the second via extends from the second conductive line to the second gate electrode and penetrates the first and second dielectric layers.