Invention Grant
- Patent Title: Compensation capacitors layout in semiconductor device
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Application No.: US17191273Application Date: 2021-03-03
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Publication No.: US11640969B2Publication Date: 2023-05-02
- Inventor: Hiroki Hosaka , Satoru Sugimoto
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L27/108 ; G11C11/401

Abstract:
Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.
Public/Granted literature
- US20220285478A1 COMPENSATION CAPACITORS LAYOUT IN SEMICONDUCTOR DEVICE Public/Granted day:2022-09-08
Information query
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