Invention Grant
- Patent Title: Buried Zener design
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Application No.: US17192060Application Date: 2021-03-04
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Publication No.: US11640997B2Publication Date: 2023-05-02
- Inventor: Saumitra Raj Mehrotra , Kejun Xia
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L29/866
- IPC: H01L29/866 ; H01L21/265 ; H01L29/66
Abstract:
A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.
Public/Granted literature
- US20220285564A1 Buried Zener Design Public/Granted day:2022-09-08
Information query
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