Invention Grant
- Patent Title: Method of forming a semiconductor structure having a gate structure electrically connected to a word line
-
Application No.: US17659493Application Date: 2022-04-18
-
Publication No.: US11641734B2Publication Date: 2023-05-02
- Inventor: Szu-Yao Chang
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: G11C8/14
- IPC: G11C8/14 ; G11C11/402 ; H01L49/02

Abstract:
A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.
Public/Granted literature
- US20220238530A1 METHOD OF FORMING SEMICONDUCTOR STRUCTURE Public/Granted day:2022-07-28
Information query