Invention Grant
- Patent Title: Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency
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Application No.: US13974571Application Date: 2013-08-23
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Publication No.: US11645083B2Publication Date: 2023-05-09
- Inventor: Christian Wiencke , Shrey Sudhir Bhatia , Jeroen Vilegen
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Krista Y. Chan; Frank D. Cimino
- Main IPC: G06F9/38
- IPC: G06F9/38
Abstract:
A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.
Public/Granted literature
- US20150058602A1 PROCESSOR WITH ADAPTIVE PIPELINE LENGTH Public/Granted day:2015-02-26
Information query
