A memory address generator for generating an address of a location in a memory includes a first address input for receiving a first address having a location in the memory being accessed during a first memory access cycle, and a next address output configured to output a next address comprising a location in the memory to be accessed during a subsequent memory access cycle based on the current address and a memory address increment value The address increment unit includes a counter arrangement and a selector arrangement, wherein each counter of the counter arrangement is configured to provide an output signal at the output indicative of a maximum value being reached and the selector arrangement is configured to provide a candidate memory address increment value based on the output of the counter arrangement as the memory address increment value output by the address increment unit.