A memory device having an improved program performance includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to program each of the plurality of memory cells to a target program state among a plurality of program states. The control logic is configured to control the peripheral circuit to apply a program voltage to a word line that is coupled to the plurality of memory cells and perform a bit line discharge operation of applying program enable voltages to a plurality of bit lines that is coupled to the plurality of memory cells while the program voltage is applied to the word line. Timings for applying the program enable voltages to the plurality of bit lines are determined based on the corresponding target program states.