Invention Grant
- Patent Title: DRAM retention test method for dynamic error correction
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Application No.: US17245491Application Date: 2021-04-30
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Publication No.: US11646090B2Publication Date: 2023-05-09
- Inventor: Ely Tsern , Frederick A Ware , Suresh Rajan , Thomas Vogelsang
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Agency: Peninsula Patent Group
- Agent Lance Kreisman
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/24 ; G06F11/10 ; G11C29/50 ; G11C5/04 ; G11C29/44

Abstract:
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
Public/Granted literature
- US20210335437A1 DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION Public/Granted day:2021-10-28
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