Invention Grant
- Patent Title: Shared error check and correct logic for multiple data banks
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Application No.: US17187124Application Date: 2021-02-26
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Publication No.: US11646092B2Publication Date: 2023-05-09
- Inventor: Susumu Takahashi , Hiroki Fujisawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/42 ; G11B20/18 ; G11C8/10 ; G11C7/10 ; G11C8/12
Abstract:
Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.
Public/Granted literature
- US20210183462A1 SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS Public/Granted day:2021-06-17
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