A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.