Invention Grant
- Patent Title: Method of fabricating semiconductor structure
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Application No.: US17538044Application Date: 2021-11-30
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Publication No.: US11646224B2Publication Date: 2023-05-09
- Inventor: Hsih-Yang Chiu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16936194 2020.07.22
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528

Abstract:
The present disclosure provides a method of fabricating a semiconductor structure with a reduced pitch (half-pitch feature) and a method of fabricating the same. The method includes providing a substrate; forming a dielectric layer disposed on the substrate; forming at least one main feature disposed in the dielectric layer and contacting the substrate; forming at least one first conductive feature disposed in the dielectric layer and on the main feature; forming at least one first spacer interposed between the dielectric layer and a portion of the first conductive feature; forming a plurality of second conductive features disposed in the dielectric layer and on either side of the first conductive feature; and forming a plurality of second spacers interposed between the dielectric layer and portions of the second conductive features.
Public/Granted literature
- US20220084876A1 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE Public/Granted day:2022-03-17
Information query
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