Invention Grant
- Patent Title: Through silicon via design for stacking integrated circuits
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Application No.: US17370045Application Date: 2021-07-08
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Publication No.: US11646308B2Publication Date: 2023-05-09
- Inventor: Kong-Beng Thei , Dun-Nian Yaung , Fu-Jier Fan , Hsing-Chih Lin , Hsiao-Chin Tuan , Jen-Cheng Liu , Alexander Kalnitsky , Yi-Sheng Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L27/06 ; H01L23/48 ; H01L23/522 ; H01L23/31 ; H01L21/48

Abstract:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
Public/Granted literature
- US20210343707A1 THROUGH SILICON VIA DESIGN FOR STACKING INTEGRATED CIRCUITS Public/Granted day:2021-11-04
Information query
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