Invention Grant
- Patent Title: Dual-layer channel transistor and methods of forming same
-
Application No.: US17228392Application Date: 2021-04-12
-
Publication No.: US11646379B2Publication Date: 2023-05-09
- Inventor: Hung Wei Li , Kuo-Chang Chiang , Mauricio Manfrini , Sai-Hooi Yeong , Yu-Ming Lin
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: The Marbury Law Group, PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/786 ; H01L29/66 ; H01L29/10

Abstract:
A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
Public/Granted literature
- US20210399141A1 DUAL-LAYER CHANNEL TRANSISTOR AND METHODS OF FORMING SAME Public/Granted day:2021-12-23
Information query
IPC分类: