Invention Grant
- Patent Title: Via-trace structures
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Application No.: US15942864Application Date: 2018-04-02
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Publication No.: US11652036B2Publication Date: 2023-05-16
- Inventor: Jeremy Ecton , Hiroki Tanaka , Kristof Kuwawi Darmawikarta , Oscar Ojeda , Arnab Roy , Nicholas Haehn
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/14 ; H01L23/00 ; H01L21/027 ; G03F7/039 ; G03F7/038 ; G03F7/20 ; G03F7/26 ; H01L21/48

Abstract:
Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.
Public/Granted literature
- US20190304890A1 ALIGNMENT VIA-TRACE STRUCTURES Public/Granted day:2019-10-03
Information query
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