Invention Grant
- Patent Title: 4F2 DRAM cell using vertical thin film transistor
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Application No.: US16013798Application Date: 2018-06-20
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Publication No.: US11653487B2Publication Date: 2023-05-16
- Inventor: Abhishek Sharma , Yih Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/786

Abstract:
Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.
Public/Granted literature
- US20190393222A1 4F2 DRAM CELL USING VERTICAL THIN FILM TRANSISTOR Public/Granted day:2019-12-26
Information query
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