Invention Grant
- Patent Title: FeFET with embedded conductive sidewall spacers and process for forming the same
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Application No.: US16700782Application Date: 2019-12-02
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Publication No.: US11653502B2Publication Date: 2023-05-16
- Inventor: Shriram Shivaraman , Seung Hoon Sung , Ashish Verma Penumatcha , Uygar E. Avci
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/51 ; H01L29/78 ; G11C11/22 ; H01L27/1159 ; H01L49/02 ; H01L27/11507 ; G11C5/06

Abstract:
A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.
Public/Granted literature
- US20210167073A1 FEFET WITH EMBEDDED CONDUCTIVE SIDEWALL SPACERS AND PROCESS FOR FORMING THE SAME Public/Granted day:2021-06-03
Information query
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