A memory controller coupled to a memory device and a host device and configured to control access operations of the memory device includes a buffer memory, a host interface, a microprocessor and a data protection engine. The host interface is coupled to the host device and configured to write data received from the host device into the buffer memory and issue a buffer memory write complete notification after the data has been written in the buffer memory. The microprocessor is configured to trigger a data protection operation in response to the buffer memory write complete notification. The protection engine is configured to perform the data protection operation to generate corresponding protection information according to the data written in the buffer memory. The microprocessor is configured to directly trigger the data protection operation after confirming that the data has been written in the buffer memory.