Invention Grant
- Patent Title: Wafer sensitivity determination and communication
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Application No.: US17378423Application Date: 2021-07-16
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Publication No.: US11657207B2Publication Date: 2023-05-23
- Inventor: Thomas Cecil
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G03F7/20 ; G06F30/398 ; G03F1/70 ; G06F30/392 ; G06F119/18

Abstract:
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.
Public/Granted literature
- US20220035240A1 WAFER SENSITIVITY DETERMINATION AND COMMUNICATION Public/Granted day:2022-02-03
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