A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.