- Patent Title: Isolating problematic memory planes to avoid neighbor plan disturb
-
Application No.: US17382424Application Date: 2021-07-22
-
Publication No.: US11657883B2Publication Date: 2023-05-23
- Inventor: Ke Zhang , Liang Li , Jiahui Yuan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/08 ; G11C16/26 ; G11C16/10

Abstract:
Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.
Public/Granted literature
- US20230023618A1 ISOLATING PROBLEMATIC MEMORY PLANES TO AVOID NEIGHBOR PLAN DISTURB Public/Granted day:2023-01-26
Information query