Invention Grant
- Patent Title: Interconnect structure with dielectric cap layer and etch stop layer stack
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Application No.: US17210015Application Date: 2021-03-23
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Publication No.: US11658064B2Publication Date: 2023-05-23
- Inventor: Chao-Chun Wang , Jen Hung Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.
Public/Granted literature
- US20220102203A1 INTERCONNECT STRUCTURE WITH DIELECTRIC CAP LAYER AND ETCH STOP LAYER STACK Public/Granted day:2022-03-31
Information query
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