Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US17567519Application Date: 2022-01-03
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Publication No.: US11658085B2Publication Date: 2023-05-23
- Inventor: Chien-Hsun Chen , Yu-Ling Tsai , Jiun Yi Wu , Chien-Hsun Lee , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/538 ; H01L23/498

Abstract:
In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
Public/Granted literature
- US20220122897A1 Integrated Circuit Package and Method Public/Granted day:2022-04-21
Information query
IPC分类: