Invention Grant
- Patent Title: Metal-oxide semiconductor (MOS) capacitor (MOSCAP) circuits and MOS device array bulk tie cells for increasing MOS device array density
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Application No.: US17088141Application Date: 2020-11-03
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Publication No.: US11658250B2Publication Date: 2023-05-23
- Inventor: Bed Raj Kandel
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm Incorporated
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L23/528 ; H01L27/10 ; H01L27/105 ; H01L29/06

Abstract:
High-density metal-oxide semiconductor (MOS) capacitor (MOSCAP) cell circuits and MOS device array circuits are disclosed. A gate comprising a selected aspect ratio disposed in a MOSCAP cell circuit comprising a cell region is configured to increase a capacitive density by increasing an extent to which metal routing layers contribute to a total MOSCAP cell circuit capacitance. An area of a MOSCAP array circuit is also reduced. Also, bulk tie cells are disposed within a MOS device array circuit in array diffusion regions to increased MOS device array circuit density. The array diffusion regions include a first device region including MOS devices and a bulk tie region including the bulk tie cells. The bulk tie region is isolated from the first device region by a diffusion cut. A diffusion cut is between a first gate on the device region and a second gate on the bulk tie region.
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