Invention Grant
- Patent Title: Semiconductor integrated circuit, receiving device, and DC offset cancellation method
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Application No.: US17412142Application Date: 2021-08-25
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Publication No.: US11658628B2Publication Date: 2023-05-23
- Inventor: Takaya Yamamoto
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP 2020156324 2020.09.17
- Main IPC: H03F3/45
- IPC: H03F3/45

Abstract:
A semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.
Public/Granted literature
- US20220085779A1 SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND DC OFFSET CANCELLATION METHOD Public/Granted day:2022-03-17
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