Invention Grant
- Patent Title: Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop
-
Application No.: US17663216Application Date: 2022-05-13
-
Publication No.: US11658667B2Publication Date: 2023-05-23
- Inventor: Raja Prabhu J , Sandeep Sasi , Harshavardhan Reddy
- Applicant: Shaoxing Yuanfang Semiconductor Co., Ltd.
- Applicant Address: CN Shaoxin
- Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
- Current Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
- Current Assignee Address: CN Shaoxing
- Agency: Phorizons PLLC
- Agent Narendra Reddy Thappeta
- Priority: IN 2141030146 2021.07.05
- Main IPC: H03L7/197
- IPC: H03L7/197 ; H03L7/099 ; H03L7/093 ; H03L7/107
Abstract:
A division factor generator of a feedback divider block in a fractional-N phase locked loop (PLL). The division factor generator is enabled to operate with larger values of division factors without increased complexity of an internal modulator core implemented, for example, as a delta-sigma modulator (DSM) having a signal transfer function (STF), wherein the STF always generates only an integer value as an output in response to an integer value received as input.
Public/Granted literature
Information query
IPC分类:
