Invention Grant
- Patent Title: Method for eliminating fake faults in gate-level simulation
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Application No.: US17002870Application Date: 2020-08-26
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Publication No.: US11668749B2Publication Date: 2023-06-06
- Inventor: Chia-Cheng Pai
- Applicant: Silicon Motion, Inc.
- Applicant Address: TW Jhubei
- Assignee: SILICON MOTION, INC.
- Current Assignee: SILICON MOTION, INC.
- Current Assignee Address: TW Jhubei
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G01R27/28
- IPC: G01R27/28 ; G01R31/317 ; G01R31/3193

Abstract:
A method for determining the propagation delay of each path in an integrated circuit is provided herein. The method includes determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement; determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement; and when the selected path exceeds the timing requirement in the path-based mode, lowering the cell delay of each cell in the selected path.
Public/Granted literature
- US20220065931A1 METHOD FOR ELIMINATING FAKE FAULTS IN GATE-LEVEL SIMULATION Public/Granted day:2022-03-03
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