Invention Grant
- Patent Title: Methods relating to circuit verification
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Application No.: US17106965Application Date: 2020-11-30
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Publication No.: US11669666B1Publication Date: 2023-06-06
- Inventor: Dantes John , Stefano Rachiele
- Applicant: Dialog Semiconductor (UK) Limited
- Applicant Address: GB London
- Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee Address: GB London
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/35 ; G06F30/3308 ; G06F30/33 ; G06F30/323
Abstract:
A method for determining one or more tests suitable for verifying that a circuit conforms to a specification is presented. The specification has at least one state machine. Example circuits are asynchronous circuits. The method includes analysing the specification to automatically determine the one or more tests for circuit verification.
Information query
