Invention Grant
- Patent Title: Via-first process for connecting a contact and a gate electrode
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Application No.: US17533434Application Date: 2021-11-23
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Publication No.: US11670544B2Publication Date: 2023-06-06
- Inventor: Chao-Hsun Wang , Mei-Yun Wang , Kuo-Yi Chao , Wang-Jung Hsueh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US16797375 2020.02.21
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L27/11 ; H01L23/522 ; H01L21/311 ; H01L23/528 ; H01L21/02 ; H01L23/532

Abstract:
Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
Public/Granted literature
- US20220093456A1 VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE Public/Granted day:2022-03-24
Information query
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