Invention Grant
- Patent Title: 3D buildup of thermally conductive layers to resolve die height differences
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Application No.: US16721802Application Date: 2019-12-19
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Publication No.: US11670561B2Publication Date: 2023-06-06
- Inventor: Zhimin Wan , Chandra Mohan Jha , Je-Young Chang , Chia-Pin Chiu , Liwei Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L23/31 ; H01L23/373 ; H01L23/42 ; H01L23/538 ; H01L25/065 ; H01L25/18 ; H01L21/48 ; H01L21/56 ; H01L25/00

Abstract:
Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.
Public/Granted literature
- US20210193547A1 3D BUILDUP OF THERMALLY CONDUCTIVE LAYERS TO RESOLVE DIE HEIGHT DIFFERENCES Public/Granted day:2021-06-24
Information query
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