Invention Grant
- Patent Title: Silicon channel tempering
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Application No.: US17097323Application Date: 2020-11-13
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Publication No.: US11670723B2Publication Date: 2023-06-06
- Inventor: Mao-Lin Huang , Lung-Kun Chu , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/092 ; H01L21/02 ; H01L29/08 ; H01L29/66 ; H01L29/786 ; H01L29/06 ; H01L29/423 ; H01L21/28 ; H01L21/8238

Abstract:
A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.
Public/Granted literature
- US20210359142A1 SILICON CHANNEL TEMPERING Public/Granted day:2021-11-18
Information query
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