Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.