A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.