A semiconductor memory device includes a substrate including a first region, as second region, a third region and a fourth regions, the first region including a memory cell array, the second region including a circuit for controlling the memory cell array, the third region separating the first region and the second region, and the fourth region surrounding the third region, a first transistor provided in the second region, a second transistor provided in the third region between the first region and the first transistor, a third transistor provided in the third region between the first transistor and the second transistor, and a first insulating layer including a first portion disposed above the first to third transistors, and a second portion disposed in contact with the substrate between the second transistor and the third transistor.