Variable resistance memory device
Abstract:
A variable resistance memory device includes lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction, peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction, and lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction. Each of the lower conductive lines includes a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion connecting the first lower extending portion to the second lower extending portion. Each of the lower contacts is in the lower connecting portion of a respective one of the lower conductive lines.
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