Systems and methods for semiconductor chip hole geometry metrology
Abstract:
In certain aspects, a method for training a model is disclosed. A model for measuring a geometric attribute of a hole structure in a semiconductor chip is provided by at least one processor. A plurality of training samples each including a pair of an optical spectrum signal and a reference signal corresponding to a same hole structure are obtained by the at least one processor. The reference signal is labeled with a labeled geometric attribute of the hole structure. An estimated geometric attribute of the hole structure is estimated using the model. A parameter of the model is adjusted based, at least in part, on a difference between the labeled geometric attribute and the estimated geometric attribute in each of the training samples by the at least one processor.
Public/Granted literature
Information query
Patent Agency Ranking
0/0