- Patent Title: Systems and methods for semiconductor chip hole geometry metrology
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Application No.: US17334394Application Date: 2021-05-28
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Publication No.: US11674909B2Publication Date: 2023-06-13
- Inventor: Le Wang , Yuanxiang Zou , Jun Zhang , Wei Zhang , Yi Zhou
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: Bayes PLLC
- Main IPC: G01N21/95
- IPC: G01N21/95 ; G01N21/21 ; G06N3/08 ; G01B11/24 ; G01N21/956 ; H01L23/538 ; H01L27/11556 ; H01L27/11582

Abstract:
In certain aspects, a method for training a model is disclosed. A model for measuring a geometric attribute of a hole structure in a semiconductor chip is provided by at least one processor. A plurality of training samples each including a pair of an optical spectrum signal and a reference signal corresponding to a same hole structure are obtained by the at least one processor. The reference signal is labeled with a labeled geometric attribute of the hole structure. An estimated geometric attribute of the hole structure is estimated using the model. A parameter of the model is adjusted based, at least in part, on a difference between the labeled geometric attribute and the estimated geometric attribute in each of the training samples by the at least one processor.
Public/Granted literature
- US20210293727A1 SYSTEMS AND METHODS FOR SEMICONDUCTOR CHIP HOLE GEOMETRY METROLOGY Public/Granted day:2021-09-23
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