Invention Grant
- Patent Title: Dedicated design for testability paths for memory sub-system controller
-
Application No.: US17545787Application Date: 2021-12-08
-
Publication No.: US11675542B2Publication Date: 2023-06-13
- Inventor: Michael Richard Spica
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F3/06 ; G06F13/16 ; G06F13/42

Abstract:
Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.
Public/Granted literature
- US20220100430A1 DEDICATED DESIGN FOR TESTABILITY PATHS FOR MEMORY SUB-SYSTEM CONTROLLER Public/Granted day:2022-03-31
Information query