Invention Grant
- Patent Title: SRAM dynamic failure handling system using CRC and method for the same
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Application No.: US17581042Application Date: 2022-01-21
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Publication No.: US11676680B2Publication Date: 2023-06-13
- Inventor: Sangsu Park
- Applicant: Magnachip Semiconductor, Ltd.
- Applicant Address: KR Chungcheongbuk-do
- Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
- Current Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
- Current Assignee Address: KR Chungcheongbuk-do
- Agency: Polsinelli PC
- Priority: KR 20210053042 2021.04.23
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C29/44 ; G11C29/12 ; G11C29/00 ; G11C29/18 ; G11C29/36

Abstract:
A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real address area.
Public/Granted literature
- US20220343991A1 SRAM DYNAMIC FAILURE HANDLING SYSTEM USING CRC AND METHOD FOR THE SAME Public/Granted day:2022-10-27
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